SCAN / EDT IMPLIMENTATION

 

1. What is compression? Advantages and Disavdantages compare with uncompressed mode
.Example.pattern count, coverage, test-time…etc?
Ans: Concept of Compression I coming in to picture when we have a very huge amount of patterns,
takes more test time, length of the chain is long. By considering some of the factor we go for
implementing compression architecture .Compression is the archtecture where the
 Internal chains length is made smaller.
 Increase the no of chains
 Also plan to have more than 1 compression if there exist more then one core.
Test compression involves compressing the amount of test data that must be stored on automatic test
equipment (ATE) for testing with a deterministic test set. This is done by adding some additional on-chip
hardware before the scan chains to decompress the test stimulus coming from the ATE and after the
scan chains to compress the response going to the ATE. Coverage will be less in lpc mode, patterns are
little more in lpc, and test time will be less because of less shift time in Lpc.

2. Without scan design, is it possible to check manufacturing faults with small circuits?
We can check the manufacturing faults using functional testcases but the amount of time takes will
be long run time weak to gather

3. What is pipeline flop? How many pipe line flops are there in top? What is the advantage of it? Is
there any extra option we use to insert a pipeline flop while insertion?
Concept of pipe –line comes to picture where there is a possiblilty of timing issue. Data coming from the
scan in to the first flop may have some delay. So by adding some pipeline flop we are syncanirizing the
data according to the rated speed required.
Pipeline flop is the one which was inserted between “scan in” pin to “scan in” pin of first flop in scan
chain and between “scan out” pin of last flop of scan chain to “scan out” pin to reduce the delay on
these long wires. Number of pipeline flops required depends on the delay between scan in pin to
flop and flop to scan out pin. We have to specify the scan clock with which the pipeline registers
needs to operate and number of pipeline registers to be used.

4. What is the clock connected to the pipeline flop?
There will be dedicated pipeline clock whose clock freq will be same as shift clock.

5. What is X tolarance and X blocking?
X blocking is the one where we insert masking logic between stump output and inputs of
compressor logic to block x-values shifted out from internal stumps and avoid corrupting scan data
outputs.

6. What is clock mixing and edge mixing? How you will achieve clock mixing and edge mixing?
Clock mixing:
When we want to merge the scan chains of two different clock domains, we use the concept of clock
mixing .This can be done by adding a lock-up latch inbetween them.
Edge Mixing:
When we have 2 different edge flops and if we want them to put in a single scan chain , we do
edge mixing these can be done in 2 ways 1) neg edge is placed first followed by pos edge 2) posedge
with lock up catch then followed bt neg edge .
Ans: If a scan chain is operating with more than one shift clock, it is called as clockmixing. In a single
scan chain contains both pos and neg edge flops is called edge mixing.By adding a latch between two
edges mixed or clock mixed flops, we can achieve it with no data loss.

7. How do you decide No.of scan chains and scan chain length?
Ans: Based on compression factor.
No of scan chains is depended on the
 How much channels the tester supports.
 Also it depends on the grouping of clocks
 Sometimes it may require some design specific requirements .(to keep the particular domain in a
separate chain )
Scan chain length is depends on
 Many factors like clock domain grouping
 Tester supported constrainsts.
 Also how muh max chain length the tester supports .

8. How do you decide the No.of test clocks?
No of test clocks can be determined by the number of functional clocks that are controlling a block.

9. What is scan chain balancing? Why it is required?
Ans: Maintaining the same length for all stumps is called scan chain balancing.It will be useful in reduce
test cost.
Scan chain balancing is the concept where a constant no or approximately equal to the nos are
maintained in the chain in order to form balanced chain.
This is required because , if there is no uniformity in the scan cell one chain will take more shift cycles as
compred to the other chain which has lesser nos of shift cycles . so because of the above reason test
time will increase .
As test cost is directly proportional to test time .

10. What are the considerations for scan?
i. Number of scan inputs and scan outputs.

ii. iii. iv. v. vi. vii.

Dedicated scan ports or shared scan ports. Compression factor. Number of shift clocks. Capture methodology is LOC or LOS. On chip clock generator or off chip clock. Clock mixing is allowed or not.

11. What are the different approaches of scan?
Ans: Top down approach and Bottom-Up approach.
Top-down approach:
It is basically doing scan insertion at the top level (ie) defining the scan port at the chip top level and
doing the scan stitching.
Bottom-up
Types of scan: Full scan, partial Scan, Partition Scan.

14. What is scan protocol? What it contains?
Ans: Scan protocol file will have the information about the scanchains and their shift (SE), testclock
information. It will have initialization setup details before entering into the testmode.

15. What is scandef file? What issues did you address in scandef file?
Scandef is the one of the optional ouput of the scan insertion tool .Basically it contains the order of
the scan chain in different format .This format is used in the scan chain re-ordering by the phyiscal
design team .

17. What are the different types of scan flops?explain functionality of each flop?and which is better to
use?
Ans:Muxed D- Scan flop , clocked Scan flop , LSSD flop.

18. What is the advantage of LSSD over mux-DFF and clocked scan?
Ans: We can avoid hold time violations using LSSD scan design method.

19. Diff b/w compression and lbist?

 20. What is compression factor for any design, how you will calculate?

Ans: compression ratio = (LPC chains)/ (1.2*no.of external chains) . It is good if it is < 30.

21. How do you achieve optimal compression ratio? Which is the compression tool used in the project?

Ans: We can get the optimal compression ratio by increasing the scan chain length, so that the no.of lpc

chins will reduce. I used DFTC Max tool for the compression.

22. Discuss diff types of compression technologies and its dis. adv and adv?

Ans: combinational XOR compression logic (DFTC MAX), sequential compression logic (EDT).

23. What is hierarchical compression flow and its adv?

Ans: If a core is having more flops (ex: more than 2lac) then we may get either high compression ratio or

high scan chain length .To avoid these kind of senarios, hierarchical compression is very useful. In

hierachical compression, first we have to compress subcore with in a core and then we compress the

total core.

24. Mention few DRC's at scan implementation phase?

Ans: D1 - clock is not controllable D2 – reset is not controllable D3-set is not controllable.

25. What is compression Ratio and vector to flop count? Explain the significance?

Ans: v2F count = (max.lpc chain length * patterns)/Total flop count V2F ratio

will give us how many patterns are required to test a single flop. If it is less than 10, will be good.

26. How do you define number of scan chains and compression ratio of the chip?

Scan chain’s in uncompresses mode is determined by tester (number of pins that it can support for

scan input and scan output).compression ratio is determined by tester memory available.

27. How do you handle multiple clocks during shifting?

Ans:We merge the clock domains during scan insertion to get balanced scan chains .so lockup latches

were added at clock domain crossing provided the skew of the second clock is less than the (clk to

Q)delay of first flop + data path delay.This was done to avoid possible data jumping during shift.

28. How many shift clocks do you have and how will you handle them?

Ans: 15 shift clocks in Top level. These will come from 15 different TCKs and will go to CRC’s, CGC’s,

CXC’s and will fed the clocks of corelevel. We can merge the clocks in scan chain

provided they are coming from same TCK.

29. If you have design with single shift clock domain and multiple capture clocks, do you need to insert

lock-up latch at clock domain crossings?

Ans: Yes. Even though there is only one shift clock, there were different clock domains and we merge

the clock domains during scan stitching to get babanced chains.There might be a skew between

different clock domains which might cause data jumping during shift.

30. Why do we need lockup latch?

Ans: we need a lockup latch between clock mixing flops and edge mixing flops in a single chain to avoid

hold time violation.

31. Lockup latch is in your design, but the first clock is skew is more than second clock will the design

work?

No it will not work.

32. If we can not insert lockup latches because of area constraint, what will you do?

Ans: we can delay the clock.

33. Is there any alternative for lock_up latch?

Lock up flop.

34. Explain why we can't put positive flops first and then negedge flops?

Because by the end of the scan cycle the dataout of both posedge flop and negedge flop will have

same value, which means that scan shift doesn’t happen properly.

35. How did you taken care the negedge flops?

Ans: Negative edge flops are stitched at the beginning of scan chain, followed by positive edge flops.

37. Give different solutions, if your design has both posedge flops and negedge flops?

Ans: 1.Negative edge flops are stitched at the beginning of scan chain, followed by positive edge flops.

2. If pos-edge flops are stitched before neg-edge flop then a lockup latch is required between them.

38. Suppose you have a design with 4 different clk domains. So in this case how do you insert scan

chains? Do you go for multiple scan chains (single scan chain/domain) or you will select single scan

cahin that covers all the modules. Discuss the adv. and dis adv?

Ans: I will go for single scan chain per domain. If we stich a single scan chain with all different clock, then

we may loss the data or flops may capture wrong values. Timing closure becomes difficult.

39. Do you have dedicated pins for scan chains or shared with functional pins?

Ans: Dedicated pins are there for scan chains.Scan pins are shared with functional pads (mostly gpio

pads).

40. How do you share functional pins for testing?

Ans. No modification is required in case of input pads, as the fanout can be used.For output

pads,modes are defined with muxes on the data and enable paths.

41. How do you go ahead in scan insertion if there are negative edge flops?

Ans: Negative edge flops are stitched at the beginning of scan chain, followed by positive edge flops.

42. How did you mix negedge and posedge flops?

Ans: Negative edge flops are stitched at the beginning of scan chain, followed by positive edge flops.

43. How top level stitching of scan chains was done?

We read the CTL’s of all the sub modules so that all the sub modules will also be a part of your top

level scan chains and also glue logic in top will also be part of your scan chain.

46. Inserted scan on RTL or netlist?

Ans: Netlist.

47. Do you know DC flow for scan insertion

Ans: YES.

BASIC INTERVIEW QUESTION ON DFT

1. What is DFT? What is the necessity of DFT in any chip? Basic Advantages?

Ans: Design For Testability is a technique which detects manufacturing defects that occurred during the course of the production. The necessity of DFT for any chip is required because if any defect occurred during the manufacturing it requires us to sort it.

2. What if the difference between DFT and Verification?

Ans: In DFT we will do structural tests and in verification they will test the functionality of the chip.

3. Can you explain the normal flow of DFT?

Ans: After getting a gate-level netlist from the synthesis team (DC netlist) the DFT flow will start.

1. MBIST RTL Generation for the Memories.
2. JTAG RTL Generation and hook up.
3. Synthesing the mbist and JTAG RTL and integrate with DC netlist.
4. Taking to the scan insertion
5. FV on pre & post DFT
6. Handoff to the PD team.
7. ATPG pattern Generation and coverage analysis.
8. Scan chain validation on post PD netlists.
9. ATPG pattern Generation on final tape out netlist.
10. Pattern Verification and handoff to a tester.

4. Explain the test cost?

Ans: Test cost depends on test time and the number of chips we can test at a time on the tester. Also the length of the longest chain and balanced effect also to consider. Test time can be reduced by reducing the number of patterns and we can test more number of chips at a time by reducing no.of pins.

5. What is meant by the test plan?

Ans: The test plan is the document that is prepared before any execution of the DFT project by the DFT Lead. This document gives us information about the

1. List of Blocks
2. Overall architecture
3. How its interlink with other blocks
4. DFT schemes that are going to be implemented.
5. Clocking Diagram
6. Reset Structure
7. Type of DFT architecture planned.
8. Clocking frequency, scan ports is it sharable or stand-alone. Type of faults targeted and their targetted frequency.
9. Limitation if any for the implementation.
10. List of DFT related ports
11. List of blocks for scan
12. If there exists any third-party IP

Planning the following things

No. Of Test clocks, No.of Scan_in and Scan_out’s, Max length of Scan chains, targetting Shift Frequency, Types of faults Targetting, Tools and Their versions.

6. Explain ASIC flow?

Ans: We need to give more explanation for DFT and PD

7. What are the tools used?

Ans: DFT Compiler, Design vision, Tetramax, Conformal LEC, ET, modelsim, PTSI

8. From the top-level how to test sub chips?

Ans: To Test subchips from the Top, we need to enable that particular core by programming coretest control module and we need to provide the information about the instance name of that particular core to the tool, so that it will add faults on that particular instance. We have to add no faults to the other cores which we are not targetting.

9. What kind of inputs should be given to a designer, so that design is DFT friendly?

Ans: All the clocks SET and RESETs should be controllable from the top-level.

10. How do you design a logic which is DFT friendly?

Ans: 

1. Need to have control on clocks of each design flop from the primary input.
2. Need to disable tri-state bus contention
3. Need to minimize redundant logic in the design
4. Synchronous and asynchronous logic must be separate

11. Explain low power DFT?

Ans: Low power DFT is a concept where we have controlling the power numbers during the shift rate. Low power DFT is the one we see in many angles .one such is how the functional logic is toggling during the shift. How we are going to limit the Toggling rate by gating enable.

 

12. On what basis EDT inserts lock-up latches?

Ans: 

1. At the decompressor side, it considers the clock edges of both edt_clock and first scan cells in the internal scan chain.
2. At the compactor side, it considers clocking of the last scan cell in the internal scan chain and the presence of pipeline stages in the compactor.
3. In bypass logic, it checks for clocking of the scan cells, which are going to be concatenated in one chain.

13. What are the EDT pins which can’t be shared with functional pins?

Ans: Except edt_clock all other EDT pins can be shared with functional pins.

14. In which cases TestKompress adds 2 latches?

Ans: TestKompress adds 2 latches in the case in which edt_clk is posedge triggered and the internal chain clock is negative edge triggered.

15. How EDT patterns look during load-unload i.e., no. of shifts required?

Ans: 

• During shift no.of shifts = scan chain length with max flops + initialization cycles.
• During Unload no.of shifts = scan chain length with maximum flops.

16. What is the scan? Why do you insert a scan in your design?

Ans: The gate-level netlist from the synthesis team will contain the flops that are having test ports (sin tied to ‘0’ and sout floating).We will stitch these flops so that every sout port is connected to sin port of other flop and divide them into no. of chains. By doing this we can have controllability and observability at each and every node. This process is called scan , and the chains here are called scan chains. If a flop is in the scan chain means the clock and reset of that flop are in our control.

17. Explain Scan Capture and Scan shift?

Ans:

Basic steps:

1. Loading the scan chains with known values.
2. Applying the Primary input
3. Observe the Primary output
4. Pulse the capture clock
5. Unload the scan chain

 

18. Is it possible to shift patterns into scan chains at a maximum frequency of 100MHz? what are the pros and cons of scan shifting?

Ans: Frequency depends on a tester , It is basically supported by tester dependency (ie). Basically we do the shifting at slow frequency .NO. Because while we are shifting all the design will be in ON state and shifting with higher frequencies will take more(IR drop) current that the circuit may not bare. If the Circuit can withstand to that much current then we can shift the patterns with 100Mhz also.

19. Why we are using a slow scan clock for a shift? What is the typical scan clock frequency?

Ans: Chip may burn if we shift with fast clock because of high IR drop. The typical shift frequency is 25MHz.

20. How many bits will be allocated for integer in Verilog?

Ans: 32

21. What kind of inputs you expect from the designers?

Ans: Clocks (Shift clocks and Capture clocks). OFF state of the clocks

1. Resets and their OFF states
2. The instances to be made as non-scan.
3. Any pre-existing Scan-chains
4. Number of Scan chains to be stitched.
5. Whether the clocks and edges to be merged
6. Whether Scan-pins to be shared with functional pins, if yes with which pins.

22. Difference between defect, fault, and failure

Ans: 

• the defect is a physical imperfection, a flaw that may lead to a fault. 
• The fault is a representation of a defect reflecting a physical condition that causes a circuit to fail to perform in a required manner.
• Failure is a deviation in the performance of a circuit or system from its specified behavior and represents an irreversible state of a component such that it must be repaired in order for it to perform the desired action.

23. What are observability and controllability?

Ans: Controllability reflects the difficulty of setting a signal line to a required logic value from primary inputs

Observability reflects the difficulty of propagating the logic value of the signal line to primary outputs.

24. What is serial and parallel loading?

Ans: Parallel patterns are forced parallel (at the same instance of time) @ SI of each flop and measured @ SO. Basically these patterns are used for simulating the patterns faster. Here only two cycles are required to simulate a pattern: one to force all the flops and one for capture.

Serial patterns are the ones that are used @the tester. They are serially shifted and captured and

shifted out.

25. Difference between sequential and combinational ATPG?

Ans: The basic difference between combinational and sequential ATPG is that, during sequential ATPG, one test vector may be insufficient to detect the target fault, because the excitation and propagation conditions may necessitate some of the flip flop values to be specified at certain values.

26. What is a fault model?

Ans: A fault model is an engineering model of something that could go wrong in the construction or operation of a piece of equipment. From the model, the designer or user can then predict the consequences of this particular fault. Fault models can be used in almost all branches of engineering.

27. How many fault models are there?

Ans: There are 6 basic categories of fault models. They are stuck at faults, transition faults, open & short faults, delay faults & cross-talk, pattern sensitivity and coupling faults, analog faults.

28. What is the difference between logic transition fault and memory transition fault?

Ans: The transition fault model also called the gross-delay fault model, is a special case of the gate-delay fault model in which the fault is assumed to be of the same order of magnitude as the clock period. 

The transition fault model is used to cover delay effects that are generated by localized defects and whose sizes are in the order of magnitude of the clock cycle or of the test pattern period. Whereas in Memory transition fault, the cell makes a transition from 0->1 and 1->0 incorrectly.

29. What is BIST?

Ans: Variety of testing challenges during wafer probe, wafer sort, pre-ship screening, incoming test of chips and boards, test of assembled boards, system test, periodic maintenance, and repair test makes testing with ATPG more expensive and time taking. The incorporation of Bist in the design stage is a solution.

Logic bist generates patterns and analyze the output responses of the functionality circuitry are embedded in the chip or somewhere on the board. 

There are two general categories of BIST 

1. On-line BIST 

2. Off-line BIST. 

Online BIST is performed when the functional circuitry is in normal operational

mode. It can be done either concurrently or nonconcurrently. 

Offline BIST is performed when the functional circuitry is not in normal mode. 

This technique does not detect any real-time errors but is widely used in the industry for testing the functional circuitry at the system, board, or chip level to ensure product quality.

INTERVIEW QUESTION ON DIGITAL ELECTRONICS-3

15. What is false path? How it determine in ckt? What the effect of false path in ckt?

Ans: By timing, all the paths in the circuit the timing analyzer can determine all the critical paths in the circuit. However, the circuit may have false paths, which are the paths in the circuit which are never exercised during normal circuit operation for any set of inputs. 

An example of a false path is shown in the figure below. The path going from the input A of the first MUX through the combinational logic out through the B input of the second MUX is a false path. This path can never be activated since if the A input of the first MUX is activated, then Sel line will also select the A input of the second MUX. STA (Static Timing Analysis) tools are able to identify simple false paths; however, they are not able to identify all the false paths and sometimes report false paths as critical paths. Removal of false paths makes circuit testable and its timing performance predictable. 

16. What is Clock Gating?
Ans: Clock gating is one of the power-saving techniques used on many synchronous circuits including the Pentium 4 processor. To save power, clock gating refers to adding additional logic to a circuit to prune the clock tree, thus disabling portions of the circuitry where flip flops do not change state. Although asynchronous circuits by definition do not have a "clock", the term "perfect clock gating" is used to illustrate how various clock gating techniques are simply approximations of the data-dependent the behavior exhibited by asynchronous circuitry and that as the granularity on which you gate the clock of a synchronous circuit approaches zero, the power consumption of that circuit approaches that of an asynchronous circuit.

17. What Physical verification?
Ans: Physical verification of the design, involves DRC (Design rule check), LVS (Layout versus schematic) Check, XOR Checks, ERC (Electrical Rule Check) and Antenna Checks.

18. Give 5 important Design techniques you would follow when doing a Layout for Digital Circuits?
Ans: 

• In digital design, decide the height of standard cells you want to layout. It depends upon how big your transistors will be. Have a reasonable width for VDD and GND metal paths. Maintaining uniform Height for all the cells is very important since this will help you use place route tool easily and also in case you want to do manual connection of all the blocks it saves on lot of areas.
• Use one metal in one direction only; this does not apply for metal 1. Say you are using metal 2 to do horizontal connections, and then use metal 3 for vertical connections, metal4 for horizontal, metal 5 vertical, etc...
• Place as much substrate contact as possible in the empty spaces of the layout.
• Do not use poly over long distances as it has huge resistances unless you have no other choice.
• Use fingered transistors as and when you feel necessary. Try maintaining symmetry in your design. Try to get the design in BIT Sliced manner.

19. Why are most interrupts active low?
Ans: This answers why most signals are active low if you consider the transistor level of a module, active low means the capacitor in the output terminal gets charged or discharged based on low to high and high to low transition respectively. When it goes from high to low it depends on the pull-down resistor that pulls it down and it is relatively easy for the output capacitance to discharge rather than charging. Hence people prefer using active low signals.

20. Give two ways of converting a two-input NAND gate to an inverter?
Ans: 

• short the 2 inputs of the NAND gate and apply the single input to it.
• Connect the output to one of the inputs and the other to the input signal.

21. How can you convert an SR Flip-flop to a JK Flip-flop?
Ans: By giving the feedback we can convert, i.e !Q=>S and Q=>R. Hence the S and R inputs will act as J and K respectively.

22. How can you convert the JK Flip-flop to a D Flip-flop?
Ans: By connecting the J input to the K through the inverter.

23. What is Race-around problem? How can you rectify it?
Ans: The clock pulse that remains in the 1 state while both J and K are equal to 1 will cause the output to complement again and repeat complementing until the pulse goes back to 0, this is called the race around problem. To avoid this undesirable operation, the clock pulse must have a time duration that is shorter than the propagation delay time of the F-F, this is restrictive so the alternative is master-slave or edge-triggered construction.

INTERVIEW QUESTION ON DIGITAL ELECTRONICS-2

5. What is the effect of the above on coverage? How to get coverage on them?
Ans: If we don’t declare them as clocks then we lose coverage on those pins. So we generally declare set and reset pins as clocks to get coverage on them.

 6. How do you design a divided by 2 clocks and will you test it?
Ans: We can use a D Flip-Flop to get divided by 2 clocks. The input clock is given to the clock pin of the D Flip-Flop. The output ~Q (i.e., NOT_Q) of the Flop is fed back to the D-pin of the flop. The signal on Q output of the flop will be divided by 2 clocks. We can write test-bench to test the design

7. How do you design divide by 3 counter?
Ans: Use two mod 2 counters. One counter designed with positive edge flops and other counter designed using negative edge flops. We can use combination of the output of these counters to get divided by 3 counter with 50% duty cycle

8. How will you check whether a number is having bit 1 in 3 rd location from LSB in a 32-bit register?
Ans: Do bitwise between 32-bit number and binary number 4 (32’b0000_0000_0000_0000_0000_0000_0000_0100). I will give the output of this operation to a 32 by 5-bit decoder.

9. What is clock feed through?
Ans: it is a special case of capacitive coupling. Like in an inverter, the coupling b/w the input and output due to Cgd. This results in an overshoot in the output voltage. The accumulation of a small positive charge on the source of a MOS switch which occurs after the switch has been turned off due to the parasitic capacitance that exists between the gate and the source of the transistor, known as clock feedthrough, is reduced by utilizing a split-gate MOS transistor, and by continuously biasing one of the gates of the split-gate transistor. Due to this, there might be an overshoot in the potential when the mosfet is switched off

10. What does u mean by a critical path?
Ans: The path through the logic which determines the ultimate speed of the structure is called the critical path. The path which has the maximum delays or the longest path in the design.

11. what is the difference between latches and flip-flops based designs
Ans: a) Latches are level-sensitive and flip-flops are edge sensitive.
b) Latch based design and flop based design is that latch allows time borrowing which a tradition flop does not. That makes latch based design more efficient. But at the same time, latch based design is more complicated and has more issues in min timing (races). Its STA with time borrowing in deep pipelining can be quite complex. Latches, physically occupy more space in the layout when compared to Flip flops. Latches occupy less area compared to flip-flops.

12. What are local-skew, global-skew, and useful-skew mean?
Ans: Local skew: The difference between the clock reaching the launching flop vs the clock reaching the destination flip-flop of a timing-path.
Global skew: The difference between the earliest reaching flip-flop and the latest reaching flip-flop for a same clock-domain.
Useful skew: Useful skew is a concept of delaying the capturing flip-flop clock path, this approach helps in meeting setup requirements within the launch and capture timing path. But the hold-requirement has to be met for the design.

13. What are the various Design constraints used while performing Synthesis for a design?
Ans:

• Create clocks (frequency, duty-cycle).
• Define the transition-time requirements for the input-ports.
• Specify the load values for the output ports
• For the inputs and the output specify the delay values (input delay and output delay), which are already consumed by the neighbour chip.
• Specify the case-setting (in case of a mux) to report the timing to specific paths.
• Specify the false-paths in the design
• Specify the multi-cycle paths in the design.
• Specify the clock-uncertainty values (w.r.t jitter and the margin values for setup/hold).

14. Difference between one-hot and binary encoding?
Ans: Common classifications used to describe the state encoding of an FSM are Binary (or highly encoded) and One hot. 

• A binary-encoded FSM design only requires as many flip-flops as are needed to uniquely encode the number of states in the state machine. The actual number of flip-flops required is equal to the ceiling of the log-base-2 of the number of states in the FSM. 
• A one-hot FSM design requires a flip-flop for each state in the design and only one flip-flop (the flip-flop representing the current or "hot" state) is set at a time in a one hot FSM design. 
• For a state machine with 9- 16 states, a binary FSM only requires 4 flip-flops while a one-hot FSM requires a flip-flop for each state in the design.
• FPGA vendors frequently recommend using a one-hot state encoding style because flip-flops are plentiful in an FPGA and the combinational logic required to implement a one-hot FSM design is typically smaller than most binary encoding styles. Since FPGA performance is typically related to the combinational logic size of the FPGA design, one-hot FSMs typically run faster than a binary encoded FSM with larger combinational logic blocks

INTERVIEW QUESTION ON DIGITAL ELECTRONICS-1

1. What is the meta-stability state?
Ans: Any circuit in an unknown state is called in the meta-stability state. It is an unstable state in which the system is not able to settle into a stable ‘0’ or ‘1’ logic level within the time required for the proper circuit operation. So that the circuit will act in unpredictable ways and leads to system failure.

Meta stability states are inherent features of Asynchronous digital systems.
In electronics, the flip flop is a device that is susceptible to Metastability state. It has two well-defined stable states ‘0 ‘ and ‘1’. But under certain conditions like Setup or Hold time violations it can however between them for more than a clock cycle. This condition is known as Metastability.

The most common cause of metastability is due to set up and hold time violation in a flip-flop. During the time from the setup to the hold (capture window) the data input of the flip-flop should remain in a stable logic state. The change of data input in that time will have a probability of setting the flop into
Metastability.

In a typical scenario where the data travels from the output of a source flop to the input of a target flop, Metastability is caused by either

a) The target flop is having a different frequency than the source flop, in which case the setup and hold time of the target flop will be violated eventually if the timing is not met between these 2 flops

b) The target and source clock is having the same frequency, but a phase alignment that causes the data to arrive at the target flop during its setup and Hold time window. This can be caused by fixed overhead and variations in logic delay times on the worst-case path between the two flops, violations in clock arrival times (clock skew) or others.

2. How to make a flop using 2 laches?
Ans: A master-slave negative edge-triggered D flip-flop is created by connecting two gated D latches in series and inverting the enable input to one of them. It is called master-slave because the second latch in the series only changes in response to a change in the first (master) latch.

3. What are the advantages and disadvantages of using synchronous reset?

Ans: Advantages: No Meta stability problem (providing recovery and removal time for reset are taken care), Simulation is easy.

Disadvantages: synchronous reset is slow; Implementation of synchronous reset requires more number of gates compared to asynchronous reset design. An active clock is essential for synchronous reset design, hence you can expect more power consumption.

4. What are the advantages and disadvantages of using an asynchronous reset?

Ans: Advantages: Implementation of asynchronous reset requires less number of gates compared to synchronous reset design, Asynchronous reset is fast, A clocking scheme is not necessary for the asynchronous design. Hence design consumes less power.

Disadvantages: Metastability problems are the main concerns of the asynchronous reset scheme (design), Static timing analysis and DFT becomes difficult due to asynchronous reset.