INTERVIEW QUESTION ON DIGITAL ELECTRONICS-3

15. What is false path? How it determine in ckt? What the effect of false path in ckt?

Ans: By timing, all the paths in the circuit the timing analyzer can determine all the critical paths in the circuit. However, the circuit may have false paths, which are the paths in the circuit which are never exercised during normal circuit operation for any set of inputs. 

An example of a false path is shown in the figure below. The path going from the input A of the first MUX through the combinational logic out through the B input of the second MUX is a false path. This path can never be activated since if the A input of the first MUX is activated, then Sel line will also select the A input of the second MUX. STA (Static Timing Analysis) tools are able to identify simple false paths; however, they are not able to identify all the false paths and sometimes report false paths as critical paths. Removal of false paths makes circuit testable and its timing performance predictable. 

16. What is Clock Gating?
Ans: Clock gating is one of the power-saving techniques used on many synchronous circuits including the Pentium 4 processor. To save power, clock gating refers to adding additional logic to a circuit to prune the clock tree, thus disabling portions of the circuitry where flip flops do not change state. Although asynchronous circuits by definition do not have a "clock", the term "perfect clock gating" is used to illustrate how various clock gating techniques are simply approximations of the data-dependent the behavior exhibited by asynchronous circuitry and that as the granularity on which you gate the clock of a synchronous circuit approaches zero, the power consumption of that circuit approaches that of an asynchronous circuit.

17. What Physical verification?
Ans: Physical verification of the design, involves DRC (Design rule check), LVS (Layout versus schematic) Check, XOR Checks, ERC (Electrical Rule Check) and Antenna Checks.

18. Give 5 important Design techniques you would follow when doing a Layout for Digital Circuits?
Ans: 

• In digital design, decide the height of standard cells you want to layout. It depends upon how big your transistors will be. Have a reasonable width for VDD and GND metal paths. Maintaining uniform Height for all the cells is very important since this will help you use place route tool easily and also in case you want to do manual connection of all the blocks it saves on lot of areas.
• Use one metal in one direction only; this does not apply for metal 1. Say you are using metal 2 to do horizontal connections, and then use metal 3 for vertical connections, metal4 for horizontal, metal 5 vertical, etc...
• Place as much substrate contact as possible in the empty spaces of the layout.
• Do not use poly over long distances as it has huge resistances unless you have no other choice.
• Use fingered transistors as and when you feel necessary. Try maintaining symmetry in your design. Try to get the design in BIT Sliced manner.

19. Why are most interrupts active low?
Ans: This answers why most signals are active low if you consider the transistor level of a module, active low means the capacitor in the output terminal gets charged or discharged based on low to high and high to low transition respectively. When it goes from high to low it depends on the pull-down resistor that pulls it down and it is relatively easy for the output capacitance to discharge rather than charging. Hence people prefer using active low signals.

20. Give two ways of converting a two-input NAND gate to an inverter?
Ans: 

• short the 2 inputs of the NAND gate and apply the single input to it.
• Connect the output to one of the inputs and the other to the input signal.

21. How can you convert an SR Flip-flop to a JK Flip-flop?
Ans: By giving the feedback we can convert, i.e !Q=>S and Q=>R. Hence the S and R inputs will act as J and K respectively.

22. How can you convert the JK Flip-flop to a D Flip-flop?
Ans: By connecting the J input to the K through the inverter.

23. What is Race-around problem? How can you rectify it?
Ans: The clock pulse that remains in the 1 state while both J and K are equal to 1 will cause the output to complement again and repeat complementing until the pulse goes back to 0, this is called the race around problem. To avoid this undesirable operation, the clock pulse must have a time duration that is shorter than the propagation delay time of the F-F, this is restrictive so the alternative is master-slave or edge-triggered construction.