INTERVIEW QUESTION ON DIGITAL ELECTRONICS-2

5. What is the effect of the above on coverage? How to get coverage on them?
Ans: If we don’t declare them as clocks then we lose coverage on those pins. So we generally declare set and reset pins as clocks to get coverage on them.

 6. How do you design a divided by 2 clocks and will you test it?
Ans: We can use a D Flip-Flop to get divided by 2 clocks. The input clock is given to the clock pin of the D Flip-Flop. The output ~Q (i.e., NOT_Q) of the Flop is fed back to the D-pin of the flop. The signal on Q output of the flop will be divided by 2 clocks. We can write test-bench to test the design

7. How do you design divide by 3 counter?
Ans: Use two mod 2 counters. One counter designed with positive edge flops and other counter designed using negative edge flops. We can use combination of the output of these counters to get divided by 3 counter with 50% duty cycle

8. How will you check whether a number is having bit 1 in 3 rd location from LSB in a 32-bit register?
Ans: Do bitwise between 32-bit number and binary number 4 (32’b0000_0000_0000_0000_0000_0000_0000_0100). I will give the output of this operation to a 32 by 5-bit decoder.

9. What is clock feed through?
Ans: it is a special case of capacitive coupling. Like in an inverter, the coupling b/w the input and output due to Cgd. This results in an overshoot in the output voltage. The accumulation of a small positive charge on the source of a MOS switch which occurs after the switch has been turned off due to the parasitic capacitance that exists between the gate and the source of the transistor, known as clock feedthrough, is reduced by utilizing a split-gate MOS transistor, and by continuously biasing one of the gates of the split-gate transistor. Due to this, there might be an overshoot in the potential when the mosfet is switched off

10. What does u mean by a critical path?
Ans: The path through the logic which determines the ultimate speed of the structure is called the critical path. The path which has the maximum delays or the longest path in the design.

11. what is the difference between latches and flip-flops based designs
Ans: a) Latches are level-sensitive and flip-flops are edge sensitive.
b) Latch based design and flop based design is that latch allows time borrowing which a tradition flop does not. That makes latch based design more efficient. But at the same time, latch based design is more complicated and has more issues in min timing (races). Its STA with time borrowing in deep pipelining can be quite complex. Latches, physically occupy more space in the layout when compared to Flip flops. Latches occupy less area compared to flip-flops.

12. What are local-skew, global-skew, and useful-skew mean?
Ans: Local skew: The difference between the clock reaching the launching flop vs the clock reaching the destination flip-flop of a timing-path.
Global skew: The difference between the earliest reaching flip-flop and the latest reaching flip-flop for a same clock-domain.
Useful skew: Useful skew is a concept of delaying the capturing flip-flop clock path, this approach helps in meeting setup requirements within the launch and capture timing path. But the hold-requirement has to be met for the design.

13. What are the various Design constraints used while performing Synthesis for a design?
Ans:

• Create clocks (frequency, duty-cycle).
• Define the transition-time requirements for the input-ports.
• Specify the load values for the output ports
• For the inputs and the output specify the delay values (input delay and output delay), which are already consumed by the neighbour chip.
• Specify the case-setting (in case of a mux) to report the timing to specific paths.
• Specify the false-paths in the design
• Specify the multi-cycle paths in the design.
• Specify the clock-uncertainty values (w.r.t jitter and the margin values for setup/hold).

14. Difference between one-hot and binary encoding?
Ans: Common classifications used to describe the state encoding of an FSM are Binary (or highly encoded) and One hot. 

• A binary-encoded FSM design only requires as many flip-flops as are needed to uniquely encode the number of states in the state machine. The actual number of flip-flops required is equal to the ceiling of the log-base-2 of the number of states in the FSM. 
• A one-hot FSM design requires a flip-flop for each state in the design and only one flip-flop (the flip-flop representing the current or "hot" state) is set at a time in a one hot FSM design. 
• For a state machine with 9- 16 states, a binary FSM only requires 4 flip-flops while a one-hot FSM requires a flip-flop for each state in the design.
• FPGA vendors frequently recommend using a one-hot state encoding style because flip-flops are plentiful in an FPGA and the combinational logic required to implement a one-hot FSM design is typically smaller than most binary encoding styles. Since FPGA performance is typically related to the combinational logic size of the FPGA design, one-hot FSMs typically run faster than a binary encoded FSM with larger combinational logic blocks