INTERVIEW QUESTION ON DIGITAL ELECTRONICS-1

1. What is the meta-stability state?
Ans: Any circuit in an unknown state is called in the meta-stability state. It is an unstable state in which the system is not able to settle into a stable ‘0’ or ‘1’ logic level within the time required for the proper circuit operation. So that the circuit will act in unpredictable ways and leads to system failure.

Meta stability states are inherent features of Asynchronous digital systems.
In electronics, the flip flop is a device that is susceptible to Metastability state. It has two well-defined stable states ‘0 ‘ and ‘1’. But under certain conditions like Setup or Hold time violations it can however between them for more than a clock cycle. This condition is known as Metastability.

The most common cause of metastability is due to set up and hold time violation in a flip-flop. During the time from the setup to the hold (capture window) the data input of the flip-flop should remain in a stable logic state. The change of data input in that time will have a probability of setting the flop into
Metastability.

In a typical scenario where the data travels from the output of a source flop to the input of a target flop, Metastability is caused by either

a) The target flop is having a different frequency than the source flop, in which case the setup and hold time of the target flop will be violated eventually if the timing is not met between these 2 flops

b) The target and source clock is having the same frequency, but a phase alignment that causes the data to arrive at the target flop during its setup and Hold time window. This can be caused by fixed overhead and variations in logic delay times on the worst-case path between the two flops, violations in clock arrival times (clock skew) or others.

2. How to make a flop using 2 laches?
Ans: A master-slave negative edge-triggered D flip-flop is created by connecting two gated D latches in series and inverting the enable input to one of them. It is called master-slave because the second latch in the series only changes in response to a change in the first (master) latch.

3. What are the advantages and disadvantages of using synchronous reset?

Ans: Advantages: No Meta stability problem (providing recovery and removal time for reset are taken care), Simulation is easy.

Disadvantages: synchronous reset is slow; Implementation of synchronous reset requires more number of gates compared to asynchronous reset design. An active clock is essential for synchronous reset design, hence you can expect more power consumption.

4. What are the advantages and disadvantages of using an asynchronous reset?

Ans: Advantages: Implementation of asynchronous reset requires less number of gates compared to synchronous reset design, Asynchronous reset is fast, A clocking scheme is not necessary for the asynchronous design. Hence design consumes less power.

Disadvantages: Metastability problems are the main concerns of the asynchronous reset scheme (design), Static timing analysis and DFT becomes difficult due to asynchronous reset.