SCAN / EDT IMPLIMENTATION

 

1. What is compression? Advantages and Disavdantages compare with uncompressed mode
.Example.pattern count, coverage, test-time…etc?
Ans: Concept of Compression I coming in to picture when we have a very huge amount of patterns,
takes more test time, length of the chain is long. By considering some of the factor we go for
implementing compression architecture .Compression is the archtecture where the
 Internal chains length is made smaller.
 Increase the no of chains
 Also plan to have more than 1 compression if there exist more then one core.
Test compression involves compressing the amount of test data that must be stored on automatic test
equipment (ATE) for testing with a deterministic test set. This is done by adding some additional on-chip
hardware before the scan chains to decompress the test stimulus coming from the ATE and after the
scan chains to compress the response going to the ATE. Coverage will be less in lpc mode, patterns are
little more in lpc, and test time will be less because of less shift time in Lpc.

2. Without scan design, is it possible to check manufacturing faults with small circuits?
We can check the manufacturing faults using functional testcases but the amount of time takes will
be long run time weak to gather

3. What is pipeline flop? How many pipe line flops are there in top? What is the advantage of it? Is
there any extra option we use to insert a pipeline flop while insertion?
Concept of pipe –line comes to picture where there is a possiblilty of timing issue. Data coming from the
scan in to the first flop may have some delay. So by adding some pipeline flop we are syncanirizing the
data according to the rated speed required.
Pipeline flop is the one which was inserted between “scan in” pin to “scan in” pin of first flop in scan
chain and between “scan out” pin of last flop of scan chain to “scan out” pin to reduce the delay on
these long wires. Number of pipeline flops required depends on the delay between scan in pin to
flop and flop to scan out pin. We have to specify the scan clock with which the pipeline registers
needs to operate and number of pipeline registers to be used.

4. What is the clock connected to the pipeline flop?
There will be dedicated pipeline clock whose clock freq will be same as shift clock.

5. What is X tolarance and X blocking?
X blocking is the one where we insert masking logic between stump output and inputs of
compressor logic to block x-values shifted out from internal stumps and avoid corrupting scan data
outputs.

6. What is clock mixing and edge mixing? How you will achieve clock mixing and edge mixing?
Clock mixing:
When we want to merge the scan chains of two different clock domains, we use the concept of clock
mixing .This can be done by adding a lock-up latch inbetween them.
Edge Mixing:
When we have 2 different edge flops and if we want them to put in a single scan chain , we do
edge mixing these can be done in 2 ways 1) neg edge is placed first followed by pos edge 2) posedge
with lock up catch then followed bt neg edge .
Ans: If a scan chain is operating with more than one shift clock, it is called as clockmixing. In a single
scan chain contains both pos and neg edge flops is called edge mixing.By adding a latch between two
edges mixed or clock mixed flops, we can achieve it with no data loss.

7. How do you decide No.of scan chains and scan chain length?
Ans: Based on compression factor.
No of scan chains is depended on the
 How much channels the tester supports.
 Also it depends on the grouping of clocks
 Sometimes it may require some design specific requirements .(to keep the particular domain in a
separate chain )
Scan chain length is depends on
 Many factors like clock domain grouping
 Tester supported constrainsts.
 Also how muh max chain length the tester supports .

8. How do you decide the No.of test clocks?
No of test clocks can be determined by the number of functional clocks that are controlling a block.

9. What is scan chain balancing? Why it is required?
Ans: Maintaining the same length for all stumps is called scan chain balancing.It will be useful in reduce
test cost.
Scan chain balancing is the concept where a constant no or approximately equal to the nos are
maintained in the chain in order to form balanced chain.
This is required because , if there is no uniformity in the scan cell one chain will take more shift cycles as
compred to the other chain which has lesser nos of shift cycles . so because of the above reason test
time will increase .
As test cost is directly proportional to test time .

10. What are the considerations for scan?
i. Number of scan inputs and scan outputs.

ii. iii. iv. v. vi. vii.

Dedicated scan ports or shared scan ports. Compression factor. Number of shift clocks. Capture methodology is LOC or LOS. On chip clock generator or off chip clock. Clock mixing is allowed or not.

11. What are the different approaches of scan?
Ans: Top down approach and Bottom-Up approach.
Top-down approach:
It is basically doing scan insertion at the top level (ie) defining the scan port at the chip top level and
doing the scan stitching.
Bottom-up
Types of scan: Full scan, partial Scan, Partition Scan.

14. What is scan protocol? What it contains?
Ans: Scan protocol file will have the information about the scanchains and their shift (SE), testclock
information. It will have initialization setup details before entering into the testmode.

15. What is scandef file? What issues did you address in scandef file?
Scandef is the one of the optional ouput of the scan insertion tool .Basically it contains the order of
the scan chain in different format .This format is used in the scan chain re-ordering by the phyiscal
design team .

17. What are the different types of scan flops?explain functionality of each flop?and which is better to
use?
Ans:Muxed D- Scan flop , clocked Scan flop , LSSD flop.

18. What is the advantage of LSSD over mux-DFF and clocked scan?
Ans: We can avoid hold time violations using LSSD scan design method.

19. Diff b/w compression and lbist?

 20. What is compression factor for any design, how you will calculate?

Ans: compression ratio = (LPC chains)/ (1.2*no.of external chains) . It is good if it is < 30.

21. How do you achieve optimal compression ratio? Which is the compression tool used in the project?

Ans: We can get the optimal compression ratio by increasing the scan chain length, so that the no.of lpc

chins will reduce. I used DFTC Max tool for the compression.

22. Discuss diff types of compression technologies and its dis. adv and adv?

Ans: combinational XOR compression logic (DFTC MAX), sequential compression logic (EDT).

23. What is hierarchical compression flow and its adv?

Ans: If a core is having more flops (ex: more than 2lac) then we may get either high compression ratio or

high scan chain length .To avoid these kind of senarios, hierarchical compression is very useful. In

hierachical compression, first we have to compress subcore with in a core and then we compress the

total core.

24. Mention few DRC's at scan implementation phase?

Ans: D1 - clock is not controllable D2 – reset is not controllable D3-set is not controllable.

25. What is compression Ratio and vector to flop count? Explain the significance?

Ans: v2F count = (max.lpc chain length * patterns)/Total flop count V2F ratio

will give us how many patterns are required to test a single flop. If it is less than 10, will be good.

26. How do you define number of scan chains and compression ratio of the chip?

Scan chain’s in uncompresses mode is determined by tester (number of pins that it can support for

scan input and scan output).compression ratio is determined by tester memory available.

27. How do you handle multiple clocks during shifting?

Ans:We merge the clock domains during scan insertion to get balanced scan chains .so lockup latches

were added at clock domain crossing provided the skew of the second clock is less than the (clk to

Q)delay of first flop + data path delay.This was done to avoid possible data jumping during shift.

28. How many shift clocks do you have and how will you handle them?

Ans: 15 shift clocks in Top level. These will come from 15 different TCKs and will go to CRC’s, CGC’s,

CXC’s and will fed the clocks of corelevel. We can merge the clocks in scan chain

provided they are coming from same TCK.

29. If you have design with single shift clock domain and multiple capture clocks, do you need to insert

lock-up latch at clock domain crossings?

Ans: Yes. Even though there is only one shift clock, there were different clock domains and we merge

the clock domains during scan stitching to get babanced chains.There might be a skew between

different clock domains which might cause data jumping during shift.

30. Why do we need lockup latch?

Ans: we need a lockup latch between clock mixing flops and edge mixing flops in a single chain to avoid

hold time violation.

31. Lockup latch is in your design, but the first clock is skew is more than second clock will the design

work?

No it will not work.

32. If we can not insert lockup latches because of area constraint, what will you do?

Ans: we can delay the clock.

33. Is there any alternative for lock_up latch?

Lock up flop.

34. Explain why we can't put positive flops first and then negedge flops?

Because by the end of the scan cycle the dataout of both posedge flop and negedge flop will have

same value, which means that scan shift doesn’t happen properly.

35. How did you taken care the negedge flops?

Ans: Negative edge flops are stitched at the beginning of scan chain, followed by positive edge flops.

37. Give different solutions, if your design has both posedge flops and negedge flops?

Ans: 1.Negative edge flops are stitched at the beginning of scan chain, followed by positive edge flops.

2. If pos-edge flops are stitched before neg-edge flop then a lockup latch is required between them.

38. Suppose you have a design with 4 different clk domains. So in this case how do you insert scan

chains? Do you go for multiple scan chains (single scan chain/domain) or you will select single scan

cahin that covers all the modules. Discuss the adv. and dis adv?

Ans: I will go for single scan chain per domain. If we stich a single scan chain with all different clock, then

we may loss the data or flops may capture wrong values. Timing closure becomes difficult.

39. Do you have dedicated pins for scan chains or shared with functional pins?

Ans: Dedicated pins are there for scan chains.Scan pins are shared with functional pads (mostly gpio

pads).

40. How do you share functional pins for testing?

Ans. No modification is required in case of input pads, as the fanout can be used.For output

pads,modes are defined with muxes on the data and enable paths.

41. How do you go ahead in scan insertion if there are negative edge flops?

Ans: Negative edge flops are stitched at the beginning of scan chain, followed by positive edge flops.

42. How did you mix negedge and posedge flops?

Ans: Negative edge flops are stitched at the beginning of scan chain, followed by positive edge flops.

43. How top level stitching of scan chains was done?

We read the CTL’s of all the sub modules so that all the sub modules will also be a part of your top

level scan chains and also glue logic in top will also be part of your scan chain.

46. Inserted scan on RTL or netlist?

Ans: Netlist.

47. Do you know DC flow for scan insertion

Ans: YES.