BASIC INTERVIEW QUESTION ON DFT

1. What is DFT? What is the necessity of DFT in any chip? Basic Advantages?

Ans: Design For Testability is a technique which detects manufacturing defects that occurred during the course of the production. The necessity of DFT for any chip is required because if any defect occurred during the manufacturing it requires us to sort it.

2. What if the difference between DFT and Verification?

Ans: In DFT we will do structural tests and in verification they will test the functionality of the chip.

3. Can you explain the normal flow of DFT?

Ans: After getting a gate-level netlist from the synthesis team (DC netlist) the DFT flow will start.

1. MBIST RTL Generation for the Memories.
2. JTAG RTL Generation and hook up.
3. Synthesing the mbist and JTAG RTL and integrate with DC netlist.
4. Taking to the scan insertion
5. FV on pre & post DFT
6. Handoff to the PD team.
7. ATPG pattern Generation and coverage analysis.
8. Scan chain validation on post PD netlists.
9. ATPG pattern Generation on final tape out netlist.
10. Pattern Verification and handoff to a tester.

4. Explain the test cost?

Ans: Test cost depends on test time and the number of chips we can test at a time on the tester. Also the length of the longest chain and balanced effect also to consider. Test time can be reduced by reducing the number of patterns and we can test more number of chips at a time by reducing no.of pins.

5. What is meant by the test plan?

Ans: The test plan is the document that is prepared before any execution of the DFT project by the DFT Lead. This document gives us information about the

1. List of Blocks
2. Overall architecture
3. How its interlink with other blocks
4. DFT schemes that are going to be implemented.
5. Clocking Diagram
6. Reset Structure
7. Type of DFT architecture planned.
8. Clocking frequency, scan ports is it sharable or stand-alone. Type of faults targeted and their targetted frequency.
9. Limitation if any for the implementation.
10. List of DFT related ports
11. List of blocks for scan
12. If there exists any third-party IP

Planning the following things

No. Of Test clocks, No.of Scan_in and Scan_out’s, Max length of Scan chains, targetting Shift Frequency, Types of faults Targetting, Tools and Their versions.

6. Explain ASIC flow?

Ans: We need to give more explanation for DFT and PD

7. What are the tools used?

Ans: DFT Compiler, Design vision, Tetramax, Conformal LEC, ET, modelsim, PTSI

8. From the top-level how to test sub chips?

Ans: To Test subchips from the Top, we need to enable that particular core by programming coretest control module and we need to provide the information about the instance name of that particular core to the tool, so that it will add faults on that particular instance. We have to add no faults to the other cores which we are not targetting.

9. What kind of inputs should be given to a designer, so that design is DFT friendly?

Ans: All the clocks SET and RESETs should be controllable from the top-level.

10. How do you design a logic which is DFT friendly?

Ans: 

1. Need to have control on clocks of each design flop from the primary input.
2. Need to disable tri-state bus contention
3. Need to minimize redundant logic in the design
4. Synchronous and asynchronous logic must be separate

11. Explain low power DFT?

Ans: Low power DFT is a concept where we have controlling the power numbers during the shift rate. Low power DFT is the one we see in many angles .one such is how the functional logic is toggling during the shift. How we are going to limit the Toggling rate by gating enable.

 

12. On what basis EDT inserts lock-up latches?

Ans: 

1. At the decompressor side, it considers the clock edges of both edt_clock and first scan cells in the internal scan chain.
2. At the compactor side, it considers clocking of the last scan cell in the internal scan chain and the presence of pipeline stages in the compactor.
3. In bypass logic, it checks for clocking of the scan cells, which are going to be concatenated in one chain.

13. What are the EDT pins which can’t be shared with functional pins?

Ans: Except edt_clock all other EDT pins can be shared with functional pins.

14. In which cases TestKompress adds 2 latches?

Ans: TestKompress adds 2 latches in the case in which edt_clk is posedge triggered and the internal chain clock is negative edge triggered.

15. How EDT patterns look during load-unload i.e., no. of shifts required?

Ans: 

• During shift no.of shifts = scan chain length with max flops + initialization cycles.
• During Unload no.of shifts = scan chain length with maximum flops.

16. What is the scan? Why do you insert a scan in your design?

Ans: The gate-level netlist from the synthesis team will contain the flops that are having test ports (sin tied to ‘0’ and sout floating).We will stitch these flops so that every sout port is connected to sin port of other flop and divide them into no. of chains. By doing this we can have controllability and observability at each and every node. This process is called scan , and the chains here are called scan chains. If a flop is in the scan chain means the clock and reset of that flop are in our control.

17. Explain Scan Capture and Scan shift?

Ans:

Basic steps:

1. Loading the scan chains with known values.
2. Applying the Primary input
3. Observe the Primary output
4. Pulse the capture clock
5. Unload the scan chain

 

18. Is it possible to shift patterns into scan chains at a maximum frequency of 100MHz? what are the pros and cons of scan shifting?

Ans: Frequency depends on a tester , It is basically supported by tester dependency (ie). Basically we do the shifting at slow frequency .NO. Because while we are shifting all the design will be in ON state and shifting with higher frequencies will take more(IR drop) current that the circuit may not bare. If the Circuit can withstand to that much current then we can shift the patterns with 100Mhz also.

19. Why we are using a slow scan clock for a shift? What is the typical scan clock frequency?

Ans: Chip may burn if we shift with fast clock because of high IR drop. The typical shift frequency is 25MHz.

20. How many bits will be allocated for integer in Verilog?

Ans: 32

21. What kind of inputs you expect from the designers?

Ans: Clocks (Shift clocks and Capture clocks). OFF state of the clocks

1. Resets and their OFF states
2. The instances to be made as non-scan.
3. Any pre-existing Scan-chains
4. Number of Scan chains to be stitched.
5. Whether the clocks and edges to be merged
6. Whether Scan-pins to be shared with functional pins, if yes with which pins.

22. Difference between defect, fault, and failure

Ans: 

• the defect is a physical imperfection, a flaw that may lead to a fault. 
• The fault is a representation of a defect reflecting a physical condition that causes a circuit to fail to perform in a required manner.
• Failure is a deviation in the performance of a circuit or system from its specified behavior and represents an irreversible state of a component such that it must be repaired in order for it to perform the desired action.

23. What are observability and controllability?

Ans: Controllability reflects the difficulty of setting a signal line to a required logic value from primary inputs

Observability reflects the difficulty of propagating the logic value of the signal line to primary outputs.

24. What is serial and parallel loading?

Ans: Parallel patterns are forced parallel (at the same instance of time) @ SI of each flop and measured @ SO. Basically these patterns are used for simulating the patterns faster. Here only two cycles are required to simulate a pattern: one to force all the flops and one for capture.

Serial patterns are the ones that are used @the tester. They are serially shifted and captured and

shifted out.

25. Difference between sequential and combinational ATPG?

Ans: The basic difference between combinational and sequential ATPG is that, during sequential ATPG, one test vector may be insufficient to detect the target fault, because the excitation and propagation conditions may necessitate some of the flip flop values to be specified at certain values.

26. What is a fault model?

Ans: A fault model is an engineering model of something that could go wrong in the construction or operation of a piece of equipment. From the model, the designer or user can then predict the consequences of this particular fault. Fault models can be used in almost all branches of engineering.

27. How many fault models are there?

Ans: There are 6 basic categories of fault models. They are stuck at faults, transition faults, open & short faults, delay faults & cross-talk, pattern sensitivity and coupling faults, analog faults.

28. What is the difference between logic transition fault and memory transition fault?

Ans: The transition fault model also called the gross-delay fault model, is a special case of the gate-delay fault model in which the fault is assumed to be of the same order of magnitude as the clock period. 

The transition fault model is used to cover delay effects that are generated by localized defects and whose sizes are in the order of magnitude of the clock cycle or of the test pattern period. Whereas in Memory transition fault, the cell makes a transition from 0->1 and 1->0 incorrectly.

29. What is BIST?

Ans: Variety of testing challenges during wafer probe, wafer sort, pre-ship screening, incoming test of chips and boards, test of assembled boards, system test, periodic maintenance, and repair test makes testing with ATPG more expensive and time taking. The incorporation of Bist in the design stage is a solution.

Logic bist generates patterns and analyze the output responses of the functionality circuitry are embedded in the chip or somewhere on the board. 

There are two general categories of BIST 

1. On-line BIST 

2. Off-line BIST. 

Online BIST is performed when the functional circuitry is in normal operational

mode. It can be done either concurrently or nonconcurrently. 

Offline BIST is performed when the functional circuitry is not in normal mode. 

This technique does not detect any real-time errors but is widely used in the industry for testing the functional circuitry at the system, board, or chip level to ensure product quality.