INTERVIEW QUESTION ON DIGITAL ELECTRONICS-3

15. What is false path? How it determine in ckt? What the effect of false path in ckt?

Ans: By timing, all the paths in the circuit the timing analyzer can determine all the critical paths in the circuit. However, the circuit may have false paths, which are the paths in the circuit which are never exercised during normal circuit operation for any set of inputs. 

An example of a false path is shown in the figure below. The path going from the input A of the first MUX through the combinational logic out through the B input of the second MUX is a false path. This path can never be activated since if the A input of the first MUX is activated, then Sel line will also select the A input of the second MUX. STA (Static Timing Analysis) tools are able to identify simple false paths; however, they are not able to identify all the false paths and sometimes report false paths as critical paths. Removal of false paths makes circuit testable and its timing performance predictable. 

16. What is Clock Gating?
Ans: Clock gating is one of the power-saving techniques used on many synchronous circuits including the Pentium 4 processor. To save power, clock gating refers to adding additional logic to a circuit to prune the clock tree, thus disabling portions of the circuitry where flip flops do not change state. Although asynchronous circuits by definition do not have a "clock", the term "perfect clock gating" is used to illustrate how various clock gating techniques are simply approximations of the data-dependent the behavior exhibited by asynchronous circuitry and that as the granularity on which you gate the clock of a synchronous circuit approaches zero, the power consumption of that circuit approaches that of an asynchronous circuit.

17. What Physical verification?
Ans: Physical verification of the design, involves DRC (Design rule check), LVS (Layout versus schematic) Check, XOR Checks, ERC (Electrical Rule Check) and Antenna Checks.

18. Give 5 important Design techniques you would follow when doing a Layout for Digital Circuits?
Ans: 

• In digital design, decide the height of standard cells you want to layout. It depends upon how big your transistors will be. Have a reasonable width for VDD and GND metal paths. Maintaining uniform Height for all the cells is very important since this will help you use place route tool easily and also in case you want to do manual connection of all the blocks it saves on lot of areas.
• Use one metal in one direction only; this does not apply for metal 1. Say you are using metal 2 to do horizontal connections, and then use metal 3 for vertical connections, metal4 for horizontal, metal 5 vertical, etc...
• Place as much substrate contact as possible in the empty spaces of the layout.
• Do not use poly over long distances as it has huge resistances unless you have no other choice.
• Use fingered transistors as and when you feel necessary. Try maintaining symmetry in your design. Try to get the design in BIT Sliced manner.

19. Why are most interrupts active low?
Ans: This answers why most signals are active low if you consider the transistor level of a module, active low means the capacitor in the output terminal gets charged or discharged based on low to high and high to low transition respectively. When it goes from high to low it depends on the pull-down resistor that pulls it down and it is relatively easy for the output capacitance to discharge rather than charging. Hence people prefer using active low signals.

20. Give two ways of converting a two-input NAND gate to an inverter?
Ans: 

• short the 2 inputs of the NAND gate and apply the single input to it.
• Connect the output to one of the inputs and the other to the input signal.

21. How can you convert an SR Flip-flop to a JK Flip-flop?
Ans: By giving the feedback we can convert, i.e !Q=>S and Q=>R. Hence the S and R inputs will act as J and K respectively.

22. How can you convert the JK Flip-flop to a D Flip-flop?
Ans: By connecting the J input to the K through the inverter.

23. What is Race-around problem? How can you rectify it?
Ans: The clock pulse that remains in the 1 state while both J and K are equal to 1 will cause the output to complement again and repeat complementing until the pulse goes back to 0, this is called the race around problem. To avoid this undesirable operation, the clock pulse must have a time duration that is shorter than the propagation delay time of the F-F, this is restrictive so the alternative is master-slave or edge-triggered construction.

INTERVIEW QUESTION ON DIGITAL ELECTRONICS-2

5. What is the effect of the above on coverage? How to get coverage on them?
Ans: If we don’t declare them as clocks then we lose coverage on those pins. So we generally declare set and reset pins as clocks to get coverage on them.

 6. How do you design a divided by 2 clocks and will you test it?
Ans: We can use a D Flip-Flop to get divided by 2 clocks. The input clock is given to the clock pin of the D Flip-Flop. The output ~Q (i.e., NOT_Q) of the Flop is fed back to the D-pin of the flop. The signal on Q output of the flop will be divided by 2 clocks. We can write test-bench to test the design

7. How do you design divide by 3 counter?
Ans: Use two mod 2 counters. One counter designed with positive edge flops and other counter designed using negative edge flops. We can use combination of the output of these counters to get divided by 3 counter with 50% duty cycle

8. How will you check whether a number is having bit 1 in 3 rd location from LSB in a 32-bit register?
Ans: Do bitwise between 32-bit number and binary number 4 (32’b0000_0000_0000_0000_0000_0000_0000_0100). I will give the output of this operation to a 32 by 5-bit decoder.

9. What is clock feed through?
Ans: it is a special case of capacitive coupling. Like in an inverter, the coupling b/w the input and output due to Cgd. This results in an overshoot in the output voltage. The accumulation of a small positive charge on the source of a MOS switch which occurs after the switch has been turned off due to the parasitic capacitance that exists between the gate and the source of the transistor, known as clock feedthrough, is reduced by utilizing a split-gate MOS transistor, and by continuously biasing one of the gates of the split-gate transistor. Due to this, there might be an overshoot in the potential when the mosfet is switched off

10. What does u mean by a critical path?
Ans: The path through the logic which determines the ultimate speed of the structure is called the critical path. The path which has the maximum delays or the longest path in the design.

11. what is the difference between latches and flip-flops based designs
Ans: a) Latches are level-sensitive and flip-flops are edge sensitive.
b) Latch based design and flop based design is that latch allows time borrowing which a tradition flop does not. That makes latch based design more efficient. But at the same time, latch based design is more complicated and has more issues in min timing (races). Its STA with time borrowing in deep pipelining can be quite complex. Latches, physically occupy more space in the layout when compared to Flip flops. Latches occupy less area compared to flip-flops.

12. What are local-skew, global-skew, and useful-skew mean?
Ans: Local skew: The difference between the clock reaching the launching flop vs the clock reaching the destination flip-flop of a timing-path.
Global skew: The difference between the earliest reaching flip-flop and the latest reaching flip-flop for a same clock-domain.
Useful skew: Useful skew is a concept of delaying the capturing flip-flop clock path, this approach helps in meeting setup requirements within the launch and capture timing path. But the hold-requirement has to be met for the design.

13. What are the various Design constraints used while performing Synthesis for a design?
Ans:

• Create clocks (frequency, duty-cycle).
• Define the transition-time requirements for the input-ports.
• Specify the load values for the output ports
• For the inputs and the output specify the delay values (input delay and output delay), which are already consumed by the neighbour chip.
• Specify the case-setting (in case of a mux) to report the timing to specific paths.
• Specify the false-paths in the design
• Specify the multi-cycle paths in the design.
• Specify the clock-uncertainty values (w.r.t jitter and the margin values for setup/hold).

14. Difference between one-hot and binary encoding?
Ans: Common classifications used to describe the state encoding of an FSM are Binary (or highly encoded) and One hot. 

• A binary-encoded FSM design only requires as many flip-flops as are needed to uniquely encode the number of states in the state machine. The actual number of flip-flops required is equal to the ceiling of the log-base-2 of the number of states in the FSM. 
• A one-hot FSM design requires a flip-flop for each state in the design and only one flip-flop (the flip-flop representing the current or "hot" state) is set at a time in a one hot FSM design. 
• For a state machine with 9- 16 states, a binary FSM only requires 4 flip-flops while a one-hot FSM requires a flip-flop for each state in the design.
• FPGA vendors frequently recommend using a one-hot state encoding style because flip-flops are plentiful in an FPGA and the combinational logic required to implement a one-hot FSM design is typically smaller than most binary encoding styles. Since FPGA performance is typically related to the combinational logic size of the FPGA design, one-hot FSMs typically run faster than a binary encoded FSM with larger combinational logic blocks

INTERVIEW QUESTION ON DIGITAL ELECTRONICS-1

1. What is the meta-stability state?
Ans: Any circuit in an unknown state is called in the meta-stability state. It is an unstable state in which the system is not able to settle into a stable ‘0’ or ‘1’ logic level within the time required for the proper circuit operation. So that the circuit will act in unpredictable ways and leads to system failure.

Meta stability states are inherent features of Asynchronous digital systems.
In electronics, the flip flop is a device that is susceptible to Metastability state. It has two well-defined stable states ‘0 ‘ and ‘1’. But under certain conditions like Setup or Hold time violations it can however between them for more than a clock cycle. This condition is known as Metastability.

The most common cause of metastability is due to set up and hold time violation in a flip-flop. During the time from the setup to the hold (capture window) the data input of the flip-flop should remain in a stable logic state. The change of data input in that time will have a probability of setting the flop into
Metastability.

In a typical scenario where the data travels from the output of a source flop to the input of a target flop, Metastability is caused by either

a) The target flop is having a different frequency than the source flop, in which case the setup and hold time of the target flop will be violated eventually if the timing is not met between these 2 flops

b) The target and source clock is having the same frequency, but a phase alignment that causes the data to arrive at the target flop during its setup and Hold time window. This can be caused by fixed overhead and variations in logic delay times on the worst-case path between the two flops, violations in clock arrival times (clock skew) or others.

2. How to make a flop using 2 laches?
Ans: A master-slave negative edge-triggered D flip-flop is created by connecting two gated D latches in series and inverting the enable input to one of them. It is called master-slave because the second latch in the series only changes in response to a change in the first (master) latch.

3. What are the advantages and disadvantages of using synchronous reset?

Ans: Advantages: No Meta stability problem (providing recovery and removal time for reset are taken care), Simulation is easy.

Disadvantages: synchronous reset is slow; Implementation of synchronous reset requires more number of gates compared to asynchronous reset design. An active clock is essential for synchronous reset design, hence you can expect more power consumption.

4. What are the advantages and disadvantages of using an asynchronous reset?

Ans: Advantages: Implementation of asynchronous reset requires less number of gates compared to synchronous reset design, Asynchronous reset is fast, A clocking scheme is not necessary for the asynchronous design. Hence design consumes less power.

Disadvantages: Metastability problems are the main concerns of the asynchronous reset scheme (design), Static timing analysis and DFT becomes difficult due to asynchronous reset.